Emerging Memory/Logic Design
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Scaling of conventional CMOS technology has been motivated by the need for higher integration density and performance over the last few decades. Static power consumption is a major concern when designing nano-scaled integrated circuits, due to the exponential dependence of subthreshold current on the threshold voltage. Embedded SRAM comprises a dominant portion of chip area, and the power consumption in modern SoCs. In SRAM cells, where the contents must be retained for long durations with a constant power supply, the subthreshold current is a significant source of power consumption. Therefore, when designing future SRAM cells for low-power applications, a vital design objective is to minimize the subthreshold current. Our goal is to use emerging technologies such as FinFET and non-volatile memories to design an ultra-energy efficient memories with high speed and density. In the following our work have been categorized to cache design in circuit and architecture and application/user levels.
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For example in our recent work, we propose CAUSE, a novel memory system based on DRAM-NVM hybrid memory architecture. CAUSE takes explicit account of the application usage patterns to distinguish data criticality and identify suitable swap candidates. We evaluate CAUSE on a real Android smartphone and using user application usage logs. Our results show CAUSE can achieve 32% faster launch time for mobile applications while reducing energy cost by 90% on average over non-optimized NVMs..
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Related Publications
[VLSI-SoC'17] J. Sim, M. Imani, Y. Kim, T. Rosing “Enabling Efficient System Design Using VerticalNanowire Transistor Current Mode Logic”, IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2017.
[DAC'17] M. Imani, S. Gupta, T. Rosing “Ultra-Efficient Processing In-Memory for Data Intensive Applications”, IEEE/ACM Design Automation Conference (DAC), 2017.
[HPCA'17] M. Imani, A. Rahimi, D. Kong, T. Rosing, J. M. Rabaey “Exploring Hyperdimensional Associative Memory”, IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2017 [PDF].
[TETC'17] M. Imani, D. Peroni, A. Rahimi, T. Rosing, “Resistive CAM Acceleration for Tunable Approximate Computing” IEEE Transactions on Emerging Topics in Computing (TETC), 2017 [PDF].
[ASP-DAC'17] M. Imani, Y. Kim, T. Rosing, “MPIM: Multi-Purpose In-Memory Processing using Configurable Resistive Memory” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2017 [PDF].
[NVMSA'16] M. Imani, A. Rahimi, Y. Kim, T. Rosing, "A Low-Power Hybrid Magnetic Cache Architecture Exploiting Narrow-Width Values" Non-Volatile Memory Systems and Applications Symposium (NVMSA), 2016 [PDF].
[ISQED'16] M. Imani, S. Patil, T. Rosing, "Low Power Data-Aware STT-RAM based Hybrid Cache Architecture" IEEE International Symposium on Quality Electronic Design (ISQED), 2016 [PDF].
[GLSVLSI'16] M. Imani, S. Patil, T. Rosing, "DCC: Double Capacity Cache for Narrow-Width Data Values" ACM Great lakes symposium on VLSI (GLSVLSI), 2016 [PDF].
[DAC'17] M. Imani, S. Gupta, T. Rosing “Ultra-Efficient Processing In-Memory for Data Intensive Applications”, IEEE/ACM Design Automation Conference (DAC), 2017.
[HPCA'17] M. Imani, A. Rahimi, D. Kong, T. Rosing, J. M. Rabaey “Exploring Hyperdimensional Associative Memory”, IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2017 [PDF].
[TETC'17] M. Imani, D. Peroni, A. Rahimi, T. Rosing, “Resistive CAM Acceleration for Tunable Approximate Computing” IEEE Transactions on Emerging Topics in Computing (TETC), 2017 [PDF].
[ASP-DAC'17] M. Imani, Y. Kim, T. Rosing, “MPIM: Multi-Purpose In-Memory Processing using Configurable Resistive Memory” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2017 [PDF].
[NVMSA'16] M. Imani, A. Rahimi, Y. Kim, T. Rosing, "A Low-Power Hybrid Magnetic Cache Architecture Exploiting Narrow-Width Values" Non-Volatile Memory Systems and Applications Symposium (NVMSA), 2016 [PDF].
[ISQED'16] M. Imani, S. Patil, T. Rosing, "Low Power Data-Aware STT-RAM based Hybrid Cache Architecture" IEEE International Symposium on Quality Electronic Design (ISQED), 2016 [PDF].
[GLSVLSI'16] M. Imani, S. Patil, T. Rosing, "DCC: Double Capacity Cache for Narrow-Width Data Values" ACM Great lakes symposium on VLSI (GLSVLSI), 2016 [PDF].
